1. Field of the Invention
The present invention relates to a solid state imaging device with a wafer-level chip size package, and more particularly to a solid state imaging device in which a wiring is extended to an opposite surface to a photoelectric conversion surface, and a producing method of the solid state imaging device.
2. Description Related to the Prior Art
A digital video camera and a video camera with use of solid state imaging device (such as CCDs, CMOS type and the like) is in wide spread use. Further, an electronic apparatus (a personal computer, a mobile phone, an electronic notepads or the like) includes a solid state imaging device and a memory to have an image-taking function. Since having a large influence on an outer size of a digital camera or an electronic apparatus with the image-taking function, the solid state imaging device is required to be small.
In order to make the solid state imaging device smaller, the solid state imaging device utilizing a packaging method called a chip size package (hereinafter CSP) is invented (for example, Japanese Utility Model Publication No. 08-005566). In the CSP method, at first, plural image sensors are formed with a matrix arrangement on the wafer in semiconductor wafer process. Then the dicing of the wafer is made, and the wafer is cut to the bare chips having respective image sensor. The bare chip is assembled on an assembly substrate, and thereafter packaged by a plastic, such that the solid state imaging device may be obtained. The obtained solid state imaging device is as large as or slightly larger than the bare chip.
Further, the solid state imaging device utilizing a wafer-level chip size package (hereinafter WLCSP) is invented to enable smaller packaging than the CSP (for example, Japanese Patent Laid-Open Publication No. 2001-351997). In the solid state imaging device with the WLCSP whose packaging is complete is obtained by making a dicing of the wafer after the image sensor are fixed with the packaging and the connection terminals are formed in the semiconductor wafer process.
The solid state imaging device of the CSP type or the WLCSP type is assembled on a printed circuit with adhesion, and a connection terminals formed on an upper face of the solid state imaging device is connected through a bonding wire to the printed circuit board. However, in this case, the assembling size actually becomes large. Accordingly, in the solid state imaging device of the above two publications No. 08-005566 and 2001-351997, the connection terminals are formed on a lower surface by through-hole interconnections and the face bonding to the assembly substrate or the printed circuit board is made.
In the above solid state imaging device of the two publications, the through-hole interconnections are formed before the bare chip are packaged with resin or a cover glass. Accordingly, dusts and cruds are easily adhered onto the imaging elements, and the production yield becomes lower. In order to solve the problems, the through-hole interconnections may be formed after the bare chip are packaged. In followings, a method of producing the solid state imaging device having the through-hole interconnections is simply explained.
For example, a solid state imaging device 100 shown in FIGS. 14A, 14B has a semiconductor substrate 103 whose upper surface is provided with image sensor 101 and contact terminals 102, and a cover glass 105 for packaging the upper face of the semiconductor substrate (sensor chip) 103 inserting a spacer 104 between the semiconductor substrate 103 and the cover glass 105. The semiconductor substrate 103 has through-hole interconnections 107 for connecting a contact terminal 102 on its upper surface to a connection terminal 106 on its lower surface. Between the semiconductor substrate 103 and the through-hole interconnections 107 and between the semiconductor substrate 103 and the connection terminal 106 are respectively provided an insulation layer 117 for insulating a side wall and an insulating layer 122 for insulating a bottom.
In the table of FIG. 15, the production process of the prior solid state imaging device 100 and a concrete content of operations in each process, and a treatment content made in each operation. The treatment content is distinguished to a high temperature treatment under high temperature, a vacuum treatment under the vacuum condition, and a wet treatment made with use of a liquid. The treatment made in each process is marked with an asterisk.
In a first process for producing the solid state imaging device 100, a joint of a wafer and a glass substrate is made. As shown in FIGS. 16A & 16B, a wafer 110 is obtained by forming plural image sensors 101 and the contact terminals 102 on the well-known silicone wafer in the semiconductor wafer process. The wafer 110 is cut into each image sensor 101 to be the semiconductor substrate (sensor chip) 103. Further, a glass substrate 111 is a substrate of the cover glass 105, and cut together with the wafer 110 to be the cover glasses 105. To a bottom of the glass substrate 111 is connected to a spacer substrate 112, which is cut in the same manner to be the spacer 104.
In order to join the wafer 110 and the glass substrate 111, an adhesive agent is applied to the spacer substrate 112. After the deposition of the spacer substrate 112 on the wafer 10, they are pressed to make the adhesion and the adhesive agent is solidified. Thus, since the image sensors are packaged by the glass substrate 111 and the spacer substrate 112, the dust does not adhere to the image sensor 101 in the following process. Note that a chain double dashed line X in this figure illustrates positions for cutting the wafer 110 and the glass substrate 111 at each image sensor 101.
In a second process, through-holes are formed. As shown in FIGS. 16C & 16D, through-holes 115 are formed on a bottom of the wafer 110 so as to confront each contact terminal 102. At first, in the portions not forming the through-holes on the bottom, a resist mask is formed by a photolithography. Then the through-holes 115 are formed on the wafer 110 by the plasma etching. Through the through-holes 115, a bottom of each contact terminal 102 is exposed. The resist mask is removed by ashing.
In the third process, the insulating layer 117 is formed on a side wall of the through-holes 115. The insulating layer 117 is formed in a chemical vapor deposition. As shown in FIG. 17A, the insulating layer 117 is formed on the contact terminal 102 exposed in the through-holes 115, and therefore prevents the conduction between the contact terminal and a conductive paste filled in the through-holes 115. Accordingly, in the fourth process, the insulation layer 117 on the contact terminal 102 is removed. In the removal of the insulation layer 117, a resist mask is formed on the bottom of the wafer 110 by a photolithography, and then the plasma etching is made to remove only the insulation layer 117 on the contact terminal which is not masked, as shown in FIG. 17B. The resist mask is removed by ashing.
In the fifth process, the through-holes 115 are filled with a conductive paste for forming the through-hole interconnections 107. The filling of the conductive paste is made by a vacuum screen printing. Then the conductive paste in the through-hole 115 is hardened by heating the wafer 110. Note that the conductive paste filled by the vacuum screen printing forms a dent on the bottom of the wafer 110. In order to modify the dent, the grinding and the polishing, namely the backgrind, is made. In the backgrind, the insulating layer 117 on the bottom of the wafer 110 is removed.
In the sixth process, an insulating layer 122 is formed on whole of the bottom of the wafer 110. At first, the plasma etching is made to whole of bottom of the wafer 110 such that the through-hole interconnections may project from the bottom as shown in FIG. 17C. Then an insulating adhesive agent is applied to a bottom of the wafer 110, and solidified with heating so as to form the insulating layer 122 in FIG. 17D. Since the insulating layer 122 is formed also on the through-hole interconnections 107, the backgrind is made again such that the through-hole interconnections 107 may be exposed from the insulation layer 122.
In a seventh process, the connection terminal 106 is formed on the insulating layer 122. In this process, a resist mask is formed on the bottom of the wafer 110 by the photolithography, and the bottom and a side of the wafer 110 is dipped into a plating solution to make an electroless deposition, such that the connection terminal 106 may be formed. In the last operation, the solution and the like are used for the removal of the resist mask. In a last eighth process, the dicing of the wafer 110 and he glass substrate 111 connected thereto is made at the position of the chain double dashed line X. The solid state imaging device 100 of the WLCSP illustrated in FIG. 14 is completed.
In order to form the through-hole interconnections in the solid state imaging device, a high-temperature treatment, a vacuum treatment, a wet treatment and the like are made many times as described above, for example a plasma etching, the ashing, a formation of the insulating layer, and the backgrind and the like. Thus, the number of the expensive operations and the total processes or operations in the production line becomes increased. Accordingly, the solid state imaging device becomes expensive.
Further, the solid state imaging device of the CSP structure or the WLCSP structure becomes small, and therefore the pitch of interconnection is short. As a result, the aspect ratio of the through-hole interconnection is high. In this case, the through-hole interconnections easily have voids caused by insufficient supply of the conductive paste, and the voids change the resistance. Especially in the solid state imaging device, the change of the resistance of the through-hole interconnection disrupts the output waveform, and the image quality became worse.